The present invention relates flash memory devices and methods of operation thereof and, more particularly, to programming of flash memory devices.
Flash memory devices are used for data storage applications in a wide variety of electronic devices, for example, in computer memory cards, solid-state storage devices (e.g., USB memory keys), digital cameras, media player devices and cellular telephones. A common flash memory type is the so called NAND flash memory, in which columns comprise serially-connected strings of floating gate transistor devices are configured to be connected to respective bit lines and have rows of control gates that are connected in parallel to common word lines.
Operations conducted on such devices typically include programming, erasing and reading. Programming of floating-gate transistor cell of a flash memory device is typically achieved by biasing the drain region of the cell to a first positive bias, relative to the source region, and biasing the control gate of the device to a second positive bias which is greater than the first positive bias. In the absence of any stored charge on the floating gate, these biases cause the formation of an inversion-layer channel of electrons at the face of the substrate, between the source and drain regions. The drain-to-source voltage accelerates these electrons through the channel to the drain region where they acquire sufficiently large kinetic energy and are typically referred to as “hot” electrons. The larger positive bias on the control gate also establishes an electrical field in a tunneling oxide layer that separates the floating gate from the channel region. This electric field attracts the hot electrons and accelerates them toward the floating gate, which is disposed between the control gate and the channel region, by a process known as tunneling. The floating gate then accumulates and traps the accumulated charge.
The accumulation of a large quantity of trapped charge (electrons) on the floating gate will cause the effective threshold voltage of the transistor to increase. If this increase is sufficiently large, the transistor will remain in a nonconductive “off” state when a predetermined “read” voltage is applied to the control gate during a read operation. In this state, known as the programmed state, the cell may be said to be storing a logic “0.” Once programmed, the device typically retains its higher threshold voltage even when its power supply is interrupted or turned off for long periods of time.
Reading of the cell may be achieved by applying a predetermined read voltage to the control gate, typically via a word line connecting a row of identical cells, and applying a positive bias to the drain region, typically via a bit line connecting a column of identical cells. If the cell is programmed, it will not conduct drain current. However, if the cell is not programmed (or has been erased), it will conduct. In this state, the cell may be said to be storing a logic “1.” Thus, by monitoring the bit line current, the state of a cell can be determined.
Erasure of a cell may be achieved by removing the stored charge from the floating gate. The erasure process can be achieved, for example, by grounding the control gate and applying a positive bias to the substrate (e.g., 10-20 Volts). Typically, flash memory devices employ bulk erasure of large numbers of cells.
As noted above, a NAND flash memory device may be arranged as plural columns including serially connected strings of cells. To program a cell within a NAND string, the bit line associated with the string is grounded. The select transistor connecting the string to a bit line is then turned “on” and all of the cells in the string other than the cell to be programmed are turned on by a applying a pass voltage (e.g., 10 volts) to their word lines sufficient to turn on the cells without causing tunneling. A higher program voltage (e.g., 18 volts) is applied to the word line of the cell to be programmed, such that tunneling occurs between the channel of the cell and its floating gate.
In a technique referred to an incremental step pulse programming (ISPP), the program voltage applied to the control gate of a cell to be programmed is incrementally increased until the cell threshold voltage reaches a desired level. In particular, the program voltage is applied at a first level, after which the threshold voltage of the cell to be programmed is checked (read) to determine whether the cell is properly programmed. If the verification fails, the program voltage is increased, followed by another round of verification. The program voltage may be incrementally increased in this manner until the desired threshold voltage is achieved. In this manner, overprogramming of the cell may be reduced or avoided.
In a NAND flash device, the word line for a cell to be programmed is also connected to cells in other strings. Typically, these other cells are biased to reduce or prevent inadvertent programming. In particular, a voltage may be applied to the channels of these “program inhibited” cells to raise their channel potentials and, thus, reduce the voltage between their channels and gate electrodes when the program voltage is applied to their control gates.
Techniques have been developed to boost channel voltages of program-inhibited cells to further reduce the likelihood of inadvertent programming. In “self-boost” techniques, cells in a non-selected string of cells are first connected to a power supply voltage via a string select transistor and bit line such that their channels are raised to the power supply voltage. Thereafter, the string select transistor turns off, and the precharged channels float. Then, when the programming voltage is applied to a selected cell and a program-inhibited cell in the non-selected string that shares the same word line, the voltage of the channel of the program-inhibited cell rises. This can help prevent the voltage between its control gate and channel from becoming sufficiently great enough to support tunneling between the channel and the floating gate electrode of the program-inhibited cell.
A potential problem with such self-boosting techniques may occur when a cell connected to the program inhibited cell has already been programmed. As noted above, programming typically increases the threshold voltage of a cell transistor. Thus, when the above-described self-boost technique is used, the channel voltage of a programmed-inhibited cell connected to an already-programmed cell may be appreciably lower than the channel voltage of a non-programmed cell when the program voltage is applied to the control gate of the program-inhibited cell. This may cause a greater voltage to develop between the control gate and the channel of the program-inhibited cell, which can lead to tunneling between the channel and the floating gate of the program-inhibited cell. Thus, inadvertent programming of the program-inhibited cell may occur, a phenomenon referred to as “program disturb.”
A technique for reducing the likelihood of program disturb is referred to as “local self-boost.” In such a technique, a lower voltage (e.g., 0 volts) is applied to the control gate of a cell adjacent the program-inhibited cell after application of the pass voltage and before application of the program voltage, such that the channel(s) of an already-programmed cell(s) is decoupled from the program-inhibited cell after the channels of the cells in the string are precharged. This allows the channel voltage of the program-inhibited cell to rise independently of the threshold voltage of the already-programmed cell when the program voltage is applied, thus limiting the voltage between the control gate and the channel of the program-inhibited cell. A potential problem of such a technique, however, is that it may require additional time for sequential application of pass and decoupling voltages, which can increase programming time. Techniques for self-boosting are described, for example, in U.S. Pat. No. 5,677,873 to Choi et al., while techniques employing local self-boosting are described in, for example, U.S. Pat. No. 5,715,194 to Hu and U.S. Pat. No. 6,061,270 to Choi.